For CS 350C
Find any mistakes? Contribute here
LDUR Xt, [Xn|SP{,#simm9}]
Read 64 bit word at memory address stored in Xn|SP optionally offset by #simm9 into Xt.
LoaD Pair of registers ISA Reference Page
LDP Xt1, Xt2, [Xn|SP{,#simm7}]
Read 2 64 bit words at memory address [Xn|SP] offset by #simm7 into Xt1 and Xt2.
The word at [Xn|SP] + #simm7 is loaded into Xt1, and the word immediately after[Xn|SP] + #simm7
is loaded into Xt2.
Note: ARM supports multiple addressing modes, chARMv3 only supports Signed Offset Addressing
STUR Xt, [Xn|SP{, #simm9}]
Write 64 bit word stored in Xt into the memory address stored in Xn|SP, offset
by #simm9
STP Xt1, Xt2, [Xn|SP{,#simm7}]
Write 2 64 bit words to memory address stored at memory address [Xn|SP] offset by #simm7 from
Xt1 and Xt2. The data in Xt1 is written at memory address [Xn|SP] + #simm7, and
the data in Xt2 is written at the next word in memory after [Xn|SP] + #simm7.
Note: ARM supports multiple addressing modes, chARMv3 only supports Signed Offset Addressing
MOVe 16 bit immediate, Keep other bits unchanged
MOVK Xd, #imm16{, LSL #hw*16}
Move the 16 bits specified in #imm16 into Xd without replacing any of the other bits.
The bits are placed at Xd[hw*16 +: 16] (verilog syntax) (i.e. if hw is zero, replace
the lsb 16 bits, if it is one, replace the next most significant bits etc..).
MOVZ Xd, #imm16{, LSL #hw*16}
Same as MOVK, except all other bits in register are zeroed out.
ADR Xd, #simm19
Load address PC + #simm19 into register Xd
form pc-relative ADdRess to 4kb Page
ADRP Xd, #simm19
Loads the base address of the page for address PC + #simm19. Same as {{PC + #simm19}[63:12], 12'h000} (verilog syntax).
CSINC Xd, Xn, Xm, cond
Copy data from either Xn or Xm + 1 to Xd based on cond. Xn is copied
if cond evaluates to true, otherwise Xm + 1 is copied.
Same as Xd = cond ? Xn : Xm + 1.
Alias to CSINC where CINC Xd, Xn, cond maps to CSINC Xd, Xn, Xn, !cond
Alias to CSINC where CSET Xd, cond maps to CSINC Xd, XZR, XZR, !cond.
CSINV Xd, Xn, Xm, cond
Copy data from either Xn or ~Xm to Xd based on cond. Xn is copied
if cond evaluates to true, and ~Xm is copied otherwise.
Same as Xd = cond ? Xn : ~Xm.
Alias to CSINV where CINV Xd, Xn, cond maps to CSINV Xd, Xn, Xn, cond;
Alias to CSINV where CSETM Xd, cond maps to CSINV Xd, XZR, XZR, !cond (XZR is the zero register)
Conditional Select NEGation (2's Compliment)
CSNEG Xd, Xn, Xm, cond
Copy data from either Xn or ~Xm + 1 to Xd based on cond. Xn is copied if
cond evaluates to true, and Xm is copied otherwise.
Same as Xd = cond ? Xn : (~Xm+1)
Alias to CSNEG where CNEG Xd, Xn, cond maps to CSNEG Xd, Xn, Xn, cond
CSEL Xd, Xn, Xm, cond
Copy data from either Xn or Xm to Xd based on cond. Xn is copied if
cond evaluates to true, otherwise Xm is copied.
Same as Xd = cond ? Xn : Xm
ADD Xd, Xn, #imm12
Adds the values of Xn and #imm12 and stores them in Xd
Does not update condition code flags
Note: ARM allows an optional shift to be specified, but chARMv3 does not
SUB Xd, Xn, #imm12
Subtracts the values of Xn and #imm12 and stores them in Xd
Does not update condition code flags
Note: ARM allows an optional shift to be specified, but chARMv3 does not
ADDS Xd, Xn, Xm
Adds the values of Xn and Xm and stores them in Xd. Updates condition code flags.
SUBS Xd, Xn, Xm
Subtracts the value of Xm from Xn and stores them in Xd. Updates condition code flags.
Alias to SUBS where CMP Xn, FSO maps to SUBS XZR, Xn, FSO ?
MVN Xd, Xm
Copies ~Xm into Xd
Does not update condition code flags
ORR Xd, Xn, Xm
Copies Xm | Xn to Xd
Does not update condition code flags
EOR Xd, Xn, Xm
Copies Xm ^ Xn to Xd
Does not update condition code flags
AND Xd|SP, Xn, #imm12
Here, you have to decode the #imm12 bitmask.
Once you have that decoded into an immediate value (we'll call it #bimm64), then store Xn & #bimm64 in Xd|SP.
Does not update condition code flags
ANDS Xd, Xn, Xm
Sets Xd to the value of Xn & Xm. Updates condition code flags.
Note: ARM allows an optional shift to be specified, but chARMv3 does not
TST Xn, Xm
Alias for ANDS, TST Xn, Xm gets mapped to ANDS XZR, Xn, Xm
Unsigned BitField Move (immediate)
UBFM Xd, Xn, #imm12r, #imm12s
#imm12r is the high 6 bits of #imm12, and #imm12s is the lower 6 bits of #imm12.
If #imm12s >= #imm12r, then #imm12s-#imm12r+1 bits are copied starting from
bit position #imm12r in Xn to the least significant bits of Xd.
If #imm12s < #imm12r, then the #imm12s+1 least significant bits of Xn
are copied to bit position 64-#imm12r of Xd
All bits outside the bitfield in both cases are set to 0.
Logical Shift Left (immediate)
Alias for UBFM, LSL Xd, Xn, #imm12 is mapped to UBFM Xd, Xn, #(-#imm6r % 64), #(63 - #imm6r)
Logical Shift Right (immediate)
Alias for UBFM, LSR Xd, Xn, #imm12 is mapped to UBFM Xd, Xn, #imm6r, #63
Signed BitField Move (immediate)
SBFM Xd, Xn, #imm12r, #imm12s
#imm12r is the high 6 bits of #imm12, and #imm12s is the lower 6 bits of #imm12.
If #imm12s >= #imm12r, then #imm12s-#imm12r+1 bits are copied starting from
bit position #imm12r in Xn to the least significant bits of Xd.
If #imm12s < #imm12r, then the #imm12s+1 least significant bits of Xn
are copied to bit position 64-#imm12r of Xd
All bits below the bitfield are set to 0, and the bits above the bitfield are all set to the MSB of the bitfield
Arithmetic Shift Right (immediate)
Alias of SBFM, ASR Xd, Xn, #imm12 maps to SBFM Xd, Xn, #imm12r, #63
B #simm26
Set PC to PC + #simm26*4
Branch to Register (unconditional)
BR Xn
Set PC to Xn
B.cond #simm19
If cond evaluates to true, set PC equal to PC + #simm19*4
BL #simm26
Set PC = PC + #simm26*4 and set X30 to PC + 4. Note that the PC value used in
the computation of X30's value is before #simm26 is added. Hint is provided
that this is a subroutine call.
BLR Xn
Set PC = Xn and set X30 to PC + 4. Note that the PC value used in
the computation of X30's value is before PC is set to Xn. Hint is provided
that this is a subroutine call.
CBNZ Xd, #simm19
If the value of Xd is nonzero, set PC to PC + #imm19*4
CBZ Xd, #simm19
If the value of Xd is zero, set PC to PC + #imm19*4
RET Xn
Set PC to Xn. When branching, a hint is specified that this is a subroutine return.
HLT
Stops the processor. Optionally can kick the processor into a debugging state.
NOP
Does the same thing as Arpan's hook throw most of the time (Nothing).